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Quad SPI-3 to SPI-4 Link Layer
Lattice Semiconductor
Bridge Core User’s Guide
The major blocks in the Quad SPI-3 to SPI-4 Bridge core are shown in Figure 2. Detailed descriptions of these
blocks follow.
Transmit Section
The transmit section can be divided into the following functional blocks:
? TX SPI-3 Interface
? Polling Sequence Controller and Polling Status Table
TX SPI-3 Interface
This block is controlled by a state machine which reads the virtual FIFOs within the DPRAMs based on the settings
in the “DPRAM Read Provisioning Registers.” The circuit operates differently based on the polling method selected,
so the two possible modes of operation will be discussed separately.
If STPA (selected-PHY transmit packet available) polling has been con?gured, then the TX block is controlled by a
state machine which alternates between two high level states. The ?rst is a polling state which checks to see if any
virtual FIFOs are empty. Also during this state it polls all PHY Layer FIFOs to determine which are below the pro-
grammed threshold. The second high level state is a read state where the circuit reads data from each virtual FIFO
in the DPRAM and transmits it to the PHY Layer device. Whenever a DPRAM FIFO contains data, it is read until a
pre-selected (programmable) number of bytes have been read or until the FIFO is empty. The “DPRAM Read Pro-
visioning Registers” have no effect when STPA has been selected.
If either DTPA or PTPA (direct transmit packet available or polled-PHY transmit packet available) are selected, then
the state machine in the TX interface circuit continuously cycles through the DPRAM virtual FIFOs, reading each
one in turn to determine if DTPA or PTPA indicate that the present port can accept data on the SPI-3. Once the
state machine begins reading a virtual FIFO, it continues reading until the virtual FIFO either goes empty or until a
pre-selected (programmable) number of bytes have been read. The order in which the virtual FIFOs are selected to
be read by the state machine is user programmable via the “DPRAM Read Provisioning Registers.” The provision-
ing registers will reset on power-up to sequentially read all virtual FIFOs which have been con?gured. If the user
wishes to turn off particular ports, then the eight registers should be written with a pattern which allocates read
cycles to the remaining ports only. For example, if four FIFOs have been con?gured, and only ports 0 and 1 are to
be enabled, then the eight registers should be programmed with a pattern of 0, 1, 0, 1, 0, 1, 0, 1 (0x00 written to
register 0x8003, 0x01 written to register 0x8004, 0x00 written to register 0x8005, etc.).
When DTPA or PTPA have been selected, then data throughput ef?ciency for a particular port is determined mainly
by the SPI-3 burst size, since a virtual FIFO will be read until it either goes empty, or until the SPI-3 burst size is
reached. The state machine will allocate a minimum of ?ve clock cycles to each port as it sequentially reads each
virtual FIFO. Therefore any ports which have no data will “waste” ?ve clock cycles each time through the rotation.
However, for the maximum burst size of 256 bytes, each FIFO containing data may be read for up to 64 clock
cycles, so ports containing data are automatically allotted more bandwidth. By setting the provisioning registers to
disable unused ports, the ?ve clock cycles which would be wasted are allocated back to the ports in use.
For both modes of operation (STPA and DTPA/PTPA) when an in-band port number is read from the DPRAM (indi-
cated by Rx_D[39] being high), then the TX SPI-3 Interface circuit will transmit the port number on the SPI-3 inter-
face and set the TSX signal. In addition, before transmitting the port number on the SPI-3 interface, the circuit will
force the next two most signi?cant bits above the port number to zeros. For example, if the core is con?gured for
eight ports per SPI-3 interface, then the port number which is transmitted on the SPI-3 in TDAT will use bits[2:0] to
identify one of eight ports, and the circuit will force bits [4:3] to zeros.
Parity is calculated and set on the TPRTY output during each word of the burst. Parity type may be set to either
even or odd and is programmable. This circuit does not use the external access to the RX Port Status Sequencer
logic which resides within the FPSC so the Rx_Ext_Status_enable signal is hardwired to 0 to disable the external
status interface.
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